divide by 3 counter_hardware synthesized

well, in my previous post i have uploaded divide by n counter
it works perfectly if you have to simulate it and show it to your teacher. but the fact is that it is not advisable for hardware synthesis because i have used always @ (clk) which means it works on both positive and negative edge triggering of clock, which is unusual for a chip
so this is my divide by 3 counter

module by3(clk,op);
input clk;
output reg op;
reg[1:0] q,t;
initial
begin
op <= 1'b0;
q <= 2'b0;
t <= 2'b0;

end
always @ (negedge clk) begin //for 3-up counter
if (q<2'b10) begin
q<=(q+1);
end else begin
q<=0;
end
end


always @ (posedge clk) begin
//to differentiate the upgoing and downgoing signals so that i can separate
// divide by 3 divides the frequency in both upgoing and downgoing pulse. so this is for upgoing pulse
if (q[0] & ~q[1])
t[1]<=~t[1];
end
always @ (negedge clk) begin //for downgoing pulse
if (~q[0] & q[1])
t[0]<=~t[0];
end

always @ (t) begin
op<= (t[0]^t[1]);
end

endmodule

module by3_tb; //testbench
reg clk;
wire op;
by3 test_bench(clk,op);
always
#1 clk = ~clk;
initial
begin
clk=1'b0;
#50 $finish;
end
initial
begin
$display("time\t\top");
$monitor("%g\t%b",$time,op);
end
initial
begin
$dumpfile("waveby3.vcd");
$dumpvars(0,by3_tb);
end
endmodule