divide by n counter using verilog

module divideC(clk,nfreq);
input clk;
output reg nfreq;
reg[2:0] counter;
initial
begin
nfreq=1'b1; //when it goes to if[line no. 12] for the first time, it jumps to line no 15. so need clk as zero first.
counter=3'b111;//so that it starts from 000 for all waves
end
always @ (clk)
begin
if (counter<=3'b011) begin //000-011=4. plus one signal due to increament. so total 5 . so divide by 5 signals.
counter<=counter+1;
end else begin
counter<=3'b0;
nfreq<= ~nfreq;
end
end
endmodule


module divideC_tb;
reg clk;
wire nfreq;
divideC test_bench(clk,nfreq);
always
#1 clk = ~clk;
initial
begin
clk=1'b0;
#50 $finish;
end
initial
begin
$display("time\t\tnFreq");
$monitor("%g\t%b",$time,nfreq);
end
initial
begin
$dumpfile("wave.vcd");
$dumpvars(0,divideC_tb);
end
endmodule